The present invention relates to complementary metal oxide semiconductor (CMOS) devices, and more particularly to metal oxide semiconductor field effect transistors (MOSFETs) that include an oxide spacer to reduce parasitic capacitance and an annealing cap that prevents dopant loss in the gate material during an activation-annealing step. The present invention also provides methods of manufacturing the CMOS devices of the present invention.
In the semiconductor industry thin, SiN spacers are typically used to implant source/drain extensions (SDE) and halos for CMOS devices. The use of SiO2 spacers is advantageous compared to SiN spacers because the lower dielectric constant of SiO2 reduces the parasitic capacitance between the gate and S/D regions.
Annealing caps are used to protect the patterned gate stack, source/drain (S/D) and SDE regions from dopant loss during activation annealing. The utilization of a deposited oxide material as the annealing cap is advantageous since low energy implantation can be performed through the bare Si substrate. After the implant, a low temperature SiO2 film may be deposited over the entire wafer to prevent dopant loss during annealing. The SiO2 cap also serves as an etch stop for the thicker SiN spacer formation used to implant the S/D regions. As in the case of the thin SiO2 spacer, the SiO2 annealing cap reduces the parasitic capacitance between the gate and S/D regions. Simulations have shown that switching from a nitride annealing cap to an oxide annealing cap improves the ring oscillation delay by as much as 5%.
A major problem of integrating thin SiO2 spacers and/or SiO2 annealing caps into prior art processes is that any SiO2 that is exposed during the pre-silicide cleaning or other process steps may be excessively etched. In the case of the thin SiO2 spacer, excessive etching may cause the entire SiO2 spacer to be removed thus leaving Si substrate area exposed. This leads to gate to substrate shorting by silicide bridging. In the case of the SiO2 annealing cap, if the etching is excessive then the thick SiN spacers are undercut and may become completely detached rendering the device inoperable. This leads to silicide bridging since the spacers are present to prevent this from occurring.
In view of the above, there is a continued need for developing a new and improved method wherein thin SiO2 spacers and/or annealing caps can be integrated into a CMOS processing flow without exhibiting any of the problems mentioned hereinabove.
One object of the present invention is to provide a method of forming a CMOS device in which a thin SiO2 spacer and/or annealing cap is employed.
Another object of the present invention is to provide a method of forming a CMOS device in which the thin SiO2 spacer and/or annealing cap is not aggressively attacked during the silicide pre-cleaning step or other process.
These and other objects and advantages are achieved in the present invention by utilizing a divot fill process which overcomes the above-mentioned drawbacks in the prior art. In accordance with the present invention, the divot fill process provides a means for protecting the exposed surfaces of the thin SiO2 spacer and/or annealing cap such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning or other process steps.
Specifically, a first method of the present invention, which forms an SiO2 annealing cap, comprises the steps of:
(a) forming an oxide film on vertical and horizontal surfaces of a semiconductor structure, said semiconductor structure comprises at least a semiconductor substrate having at least one patterned gate stack region formed thereon;
(b) forming thick spacers on portions of said oxide film that are adjoining said at least one patterned gate stack region, said thick spacers being composed of a dielectric material other than an oxide;
(c) recessing said oxide film so as to form at least a divot region between said thick spacers and a top surface of said patterned gate stack region; and
(d) forming a divot fill material in said divot region, said divot fill material being composed of a dielectric material other than an oxide. Note that in the first method of the present invention, the oxide film remaining in the structure after the recessing step is in the shape of the letter xe2x80x9cLxe2x80x9d. Hence, the oxide film remaining in the structure after recessing is present on portions of the vertical sidewalls of the patterned gate stack region as well as on a portion of the semiconductor substrate.
The first method of the present invention provides a CMOS device which comprises:
a semiconductor structure having at least one patterned gate stack region formed thereon, said patterned gate stack region having vertical sidewalls;
an oxide film formed on portions of said vertical sidewalls of said at least one patterned gate stack region as well as portions of said semiconductor substrate;
thick spacers formed on said oxide film, wherein said thick spacers extend beyond edges of said oxide film such that a divot region is present between at least said thick spacers and a top surface of said patterned gate stack region; and
a divot fill material present in said divot region.
A second method of the present invention, which forms a thin SiO2 spacer and/or annealing cap comprises the steps of:
(a) forming an oxide film on vertical and horizontal surfaces of a semiconductor structure, said semiconductor structure comprises at least a semiconductor substrate having at least one patterned gate stack region formed thereon;
(b) etching said oxide film so as to remove said oxide fill from said horizontal surfaces of said structure;
(c) forming thick spacers on portions of said oxide film that are adjoining said at least one patterned gate stack region, said thick spacers being composed of a dielectric material other than an oxide;
(d) recessing said oxide film so as to form at least a divot region between said thick spacers and a top surface of said patterned gate stack region; and
(e) forming a divot fill material in said divot region, said divot fill material being composed of a dielectric material other than an oxide.
The second method of the present invention provides a CMOS device which comprises:
a semiconductor structure having at least one patterned gate stack region formed thereon, said patterned gate stack region having vertical sidewalls;
an oxide film formed on portions of said vertical sidewalls of said at least one patterned gate stack region;
thick spacers formed on said oxide film and said semiconductor substrate, wherein said thick spacers extend beyond edges of said oxide film such that a divot region is present between at least said thick spacers and a top surface of said patterned gate stack region; and
a divot fill material present in said divot region.